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Milan X with 3D V-Cache: AMD plans Epyc series CPUs with 768 MB L3 cache

Sep 16, 2021

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AMD had already flirted with the announcement of the Ryzen 5000, which had been supplemented by a stacked L3 cache, that the technology would also work well in server CPUs. Rumors spread on Twitter now indicate: Milan will be reissued as Milan X with 768 MB L3 cache, of which 512 MB 3D V cache.

3D V-Cache is already official for Ryzen 5000

It is officially known that AMD will start producing Ryzen 5000 processors this year which not only contain the 32 MB L3 cache exposed to date per 8-core chiplet (CCD), but also an additional 64 MB per CCD. So per CCD there is 32 MB + 64 MB = 96 MB cache, a Ryzen 5000 with 16 cores and thus two CCDs comes to 192 MB in total [2 × (32 MB + 64 MB)].

Milan X achieves 768 MB L3 cache with 8 CCDs

With Milan X, AMD appears to be using the same technology in the near future for an expansion of the Epyc series based on the Milan architecture (chiplet I/O die approach with Zen 3), obviously with an unchanged basis. At the top, based on a 64-core processor with 8 CCDs, 8 × (32 MB + 64 MB) = 768 MB L3 cache are possible.

At least that's what the usually accurate Twitter user ExecutableFix claims and has named four potential Milan X models by name in this context: Epyc 7773X, 7573X, 7473X and 7373X with 64, 32, 24 and 16 cores, respectively. The following table contains these models as well as the other Milan processors available so far.

Model cores/threads base cycle/max. Turbo L3 cache DDR4 (1DPC) TDP (default) cTDP Min/Max price Colportier Milan-X models (rumor) Epyc 7773X 64/128 2.20/3.50 768 MB 3200 MHz 280 W? ? Epyc 7573X 32/64 2.80/3.60 768 MB 3200 MHz 280 W? ? Epyc 7473X 24/48 2.80/3.70 768 MB 3200 MHz 240 W? ? Epyc 7373X 16/32 3.05/3.80 768 MB 3200 MHz 240 W? ? Regular Milan models for 2-socket systems Epyc 7763 64/128 2.45/3.50 256 MB 3200 MHz 280 W 225 W/280 W $ 7,890 Epyc 7713 64/128 2.00/3.675 256 MB 3200 MHz 225 W 225 W/240 W $ 7,060 Epyc 7663 56/112 2.00/3.50 256 MB 3200 MHz 240 W 225 W/240 W $ 6,366 Epyc 7643 48/96 2.30/3.60 256 MB 3200 MHz 225 W 225 W/240 W $ 4,995 Epyc 7543 32/64 2.80/3.70 256 MB 3200 MHz 225 W 225 W/240 W $ 3,761 Epyc 7513 32/64 2.60/3.65 128 MB 3200 MHz 200 W 165 W/200 W $ 2,840 Epyc 7453 28/56 2.75/3.45 64 MB 3200 MHz 225 W 225 W/240 W $ 1,570 Epyc 7443 24/48 2.85/4.00 128 MB 3200 MHz 200 W 165 W/200 W $ 2,010 Epyc 7413 24/48 2.65/3.60 128 MB 3200 MHz 180 W 165 W/200 W $ 1,825 Epyc 7343 16/32 3.20/3.90 128 MB 3200 MHz 190 W 165 W/200 W $ 1,565 Epyc 7313 16/32 3.00/3.70 128 MB 3200 MHz 155 W 155 W/180 W $ 1,083 Milan-F models with maximum L3 cache Epyc 75F3 32/64 2.95/4.00 256 MB 3200 MHz 280 W 225 W/280 W $ 4,860 Epyc 74F3 24/48 3.20/4.00 256 MB 3200 MHz 240 W 225 W/240 W $ 2,900 Epyc 73F3 16/32 3.50/4.00 256 MB 3200 MHz 240 W 225 W/240 W $ 3,521 Epyc 72F3 8/16 3.70/4.10 256 MB 3200 MHz 180 W 165 W/200 W $ 2,468 M-lan-P models for 1-socket systems Epyc 7713P 64/128 2 .00/3.675 256 MB 3200 MHz 225 W 225 W/240 W $ 5,010 Epyc 7543P 32/64 2.80/3.70 256 MB 3200 MHz 225 W 225 W/240 W $ 2,730 Epyc 7443P 24/48 2.85/4 .00 128 MB 3200 MHz 200 W 165 W/200 W $ 1,337 Epyc 7313P 16/32 3.00/3.70 128 MB 3200 MHz 155 W 155 W/180 W $ 913

768 MB L3 from 16 to 64 cores

When looking at the four SKUs, it is noticeable that they should all use the full 768 MB L3 cache, which – if Milan X only turns the Milan architecture upside down – only works if even the 16-core Epyc 7373X processor is still available carries all 8 CCDs, but only two out of eight cores are active per CCD. AMD has already followed this approach with Milan: The F models, like the largest 8 CCD expansion stages, offer the full 256 MB because all eight CCDs can be found on the package – down to the CPU with only 16 of 64 active cores.

This is behind AMD's 3D-V-cache technology

At the presentation of the 3D V-Cache technology at the virtual Computex in June, AMD had already spoken about the technology in detail. The 64 MB additional cache takes up a base area of 6 × 6 mm in the CCD, making it as large as the 32 MB L3 cache that is already in place. With its two 32 MB layers, the new CCD has a triple stacked L3 cache module with 96 MB.

The attached L3 cache is a native 64 MB chip, it still functions as a direct extension of the existing L3 cache in the CCD, which does not require any software adjustments, as it has no control functions and for all of the units required for the basic functionality can come along. Since these are already in place, AMD can accommodate 64 MB of pure SRAM in the same space as 32 MB before. Zen 3 was already prepared for this possibility from the start, and development and implementation with partner TSMC took several years, AMD explained.

The stacking technology is based on TSVs like them are already used in various stacking solutions. The chip bonding takes place via direct contact of the copper layers, no additional BGA contact areas or the like, such as those provided by Intel's approach with stacking.

In order to use the additional L3 cache on the To accommodate the CCD without changing the height, the CCDs of the relevant processors will be thinner in the future, in order to be just as high as the I/O die in the end with the stacked additional cache and to ultimately fit under the heat spreader.