Intel Xeon Max: Sapphire Rapids with 64GB HBM offers 56 cores at 350W

Sapphire Rapids with HBM becomes the “Xeon Max Series”, Ponte Vecchio becomes the “Data Center GPU Max Series”. Intel revealed this at the supercomputing conference SC22. Intel's building blocks for HPC are thus fixed on paper. Intel has also brought further technical details with it.

Intel Sapphire Rapids comes before AMD Genoa

The timing of Intel's announcement is surprising at first glance, after all, the Supercomputing Conference won't start until next week. But Intel is already putting its own products in the spotlight today because its competitor AMD will present the Epyc CPUs with Genoa architecture on a Zen 4 basis with up to 96 cores on Thursday. In terms of top performance, the cards should then be reshuffled. Intel preempts the shuffling and also primarily plays cards apart from pure CPU performance.

Intel Xeon Max at a glance (image: Intel)

Memorybandwidth comes into focus

Intel wants Sapphire Rapids with HBM (64 GB HBM2e to start) to become the new standard for HPC systems (High Performance Computing). These CPUs address one of the biggest pain points: memory bandwidth. Intel even cites the creator of the Riken-Fugaku supercomputer, who was at the top of the Supercomputer Top500 several times. For the first time, the Riken Fugaku did not rely on maximum CPU performance, but also focused much more on the memory system and a balanced bandwidth, so that cores or other parts of the system, which are theoretically extremely fast on their own, do not starve because data is not available or cannot be brought in quickly enough. With Sapphire Rapids with HBM on the CPU package, Intel wants to take the same line and has given this expansion stage its own name with Intel Xeon Max.

The Riken boss explains HBM as a big bonus (image: Intel)

Intel Xeon Max: HBM and up to 56 cores

Intel Xeon Max is offered with up to 56 cores at a TDP of 350 watts. The well-known features such as PCIe 5.0, CXL 1.1 and a new platform that uses eight-channel DDR5 memory are included. However, Xeon Max is only intended as a dual-socket solution, regular Sapphire Rapids will later also be found in four or eight sockets.

When asked why Xeon Max didn't use the full configuration of the dies with 60 cores, the manufacturer once again explained that this was due to the binning: 56 cores would maximize the product of cores and clock in the specified TDP range. In all probability, there will be 60 cores for the Xeon Platinum in the normal series without HBM, which will be presented on January 9th.

First for supercomputers, then to OEMs

However, Xeon Max will also only be freely available from the second quarter, because the first chips delivered will go to supercomputers in the coming months. Also included is Sunspot, a kind of small Aurora with 128 blades. Researchers can use this to test the possibilities at the end of this year in order to scale them up later. Other future supercomputers are set to become “Crossroads” at Los Alamos National Laboratory, “CTS-2” at Lawrence Livermore National Laboratory and Sandia National Laboratory and “Camphor3” at Kyoto University.

Intel Xeon Max at a glance (image: Intel)

Split Intel Xeon Max (Image: Intel)

Intel Xeon Max with many accelerators included (Picture: Intel)

Intel Xeon Max with a lot of hardware optimization (Picture: Intel)

Intel Xeon Max with NUMA or UMA mode (Image: Intel)

Benchmarks from the manufacturer show fillet pieces

In addition to the technical data, Intel also has many benchmarks in its luggage. Intel is pitting the new 56-core processor against AMD's Epyc 7773X, i.e. the Milan X processor with 786 MB of stacked L3 cache, sometimes in single form and sometimes in double form. Intel also compares Ice Lake-SP, its own predecessor.

Of course, only the tests that suit the new processor are used, i.e. those that can benefit from the memory bandwidth or the additional instructions or accelerators of the CPU. In these applications, the performance increases are sometimes very large, not only compared to AMD's processor, but also in-house.

Intel Xeon Max vs AMD Epyc and Intel Ice Lake-SP (Image: Intel)

In response to criticism of the increasing consumption of Intel processors in the server segment (Ice Lake-SP was a maximum of 270 watts), Intel also addresses this aspect in its own test results – with very good results, of course. Compared to the predecessor, Intel sometimes promises more than half the consumption with the same performance thanks to optimization and HBM. This is possible because, in the best case, only one instead of four nodes is required to achieve the same performance, and Xeon Max could also be used without DDR5 memory if the 64 GB HBM2e per CPU is sufficient. In this context, when asked, Intel explained that most of the benchmark increases are also boosted by HBM.

The same performance is possible with significantly lower consumption (Picture: Intel)

Intel Xeon Max vs AMD Epyc (Picture: Intel)

Many OEM/ODM customers are there

In addition to the supercomputer customers, Intel names almost every major server manufacturer as a partner for Intel Xeon Max. That is not surprising, after all Intel is still the clear market leader in the server area, so every well-known provider will offer at least a handful of systems have to fetch.

Some of these systems will also be equipped with Ponte Vecchio, the new Intel Data Center Max Series GPU. Details are summarized in the separate message “Intel Data Center GPU Max: Ponte Vecchio starts for supercomputers in 3 variants”.

Designs from major OEMs and ODMs (image : Intel)

The future combines building blocks: Falcon Shores

Intel sees the future in XPUs that combine Xe and x86 cores in one package. This architecture will also be able to address Intellectual Property (IP) in the form of chips from other customers on the package. It is to be manufactured by the in-house Foundry IDM 2.0, Intel wants to keep all the reins in its hands if possible.

Intel Falcon Shores (Image: Intel)

ComputerBase has received information about this article from Intel under NDA. The only requirement was the earliest possible publication date.