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Intel Data Center GPU Max: Ponte Vecchio starts in 3 variants for supercomputers

Nov 9, 2022

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Intel is launching three variants for supercomputers based on the Xe-HPC-GPU Ponte Vecchio, one of them as a classic 300-watt PCIe card. However, the main focus is on the OAM modules, which are significantly more powerful at 450 or even 600 watts. The successor Rialto Bridge has already been considered.

Ponte Vecchio has been officially talked about for more than two years, now the Xe-HPC-GPU designed for supercomputers is being launched . Not only is the large flagship chip with its 47 tiles and several billion transistors included, but surprisingly also a smaller, almost half version.

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Three model variants to start with

Intel will launch three variants:

Max Series 1100 GPU: 300-watt PCIe card with 56 Xe cores and 48GB HBM2e
Max Series 1350 GPU: 450W OAM module with 112 Xe cores and 96GB HBM.
Max Series 1550 GPU: 600W OAM module with 128 Xe cores and 128 GB HBM.

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When asked, Intel explained that the PCIe card uses half a chip. In technical terms, this means that the GPU uses 1 stack, while the full expansion uses 2 stacks.

All the numbers provided by Intel below always refer to the 2-stack design in full configuration, the PCIe card, on the other hand, physically offers exactly half: A maximum of 64 cores and 204 MB L2 cache, the HBM memory is also halved. Ultimately, however, the accelerator card does not implement the full configuration of this half chip, but a slightly slimmed down version with 56 cores and 48 GB HBM.

Imposing full expansion with high performance

Expressed in bare numbers, the full expansion remains extremely impressive, not only in terms of the number of transistors & Co. Intel particularly likes to list the various caches, not only the 64 MB L1 cache, but above all the L2 cache, which can be up to 408 MB in size. Intel underpins the fact that this cache brings performance advantages with a selected test.

The goal pursued by the balanced hierarchy of register files, cache and HBM is the same as with the processors of the new Xeon Max series with HBM: data should be kept closer to the cores so that they are available faster and can be edited. In these cases, this GPU solution easily manages to cope with an Nvidia A100, Intel wants to convey. In the benchmarks shown, however, it also helps that Nvidia's Ampere alternative is sometimes only equipped with 40 GB, which once again makes it clear that manufacturer benchmarks should always be treated with caution.

This also applies to another aspect: the true opponent for Ponte Vecchio is probably Nvidia Hopper in the form of the H100 GPU. The meeting of both solutions will not take place on the free market until 2023, because all Max accelerator solutions should not be available to everyone until January 2023. In this case, too, the first GPUs delivered will migrate to the nodes for the Aurora supercomputer, work on which is already underway.

China version with lower I/O bandwidth

Right at the start of Ponte Vecchio, Intel is keeping an eye on the US government's China sanctions, which have recently been enforced. Intel from Ponte Vecchio will offer a variant that, according to the manufacturer, provides “lower I/O bandwidth to meet the needs of different markets”. This particular variant follows the notch that Nvidia had opened up with the new A800, which is an A100 with a reduced bandwidth of the NV link for China.

The successor Rialto Bridge won't come until 2024

Intel also had some information on the successor today, although most of it was already mentioned at the last supercomputer event in Hamburg at the end of May. What is new is that the next generation as an OAM module will have a TDP of up to 800 watts.

And there was also news about the date: instead of mid-2023, as it was called in May of this year, the chip will come much later in 2024. On the one hand, this is probably due to the long delay from Ponte Vecchio, which is now de facto only 2023, but also on the optimization potential of the solutions.

ComputerBase has information n received this article from Intel under NDA. The only requirement was the earliest possible publication date.