The Chinese newcomer among the manufacturers of flash memory for SSDs and smartphones is also presenting a new generation of 3D NAND at the Flash Memory Summit 2022. YMTC calls this X3-9070 and advertises the new Xtacking 3.0 architecture. The fact that the number of layers is kept secret is amazing.
X3-9070 stands for TLC
The memory named X3-9070 is TLC-NAND with 3 bits per memory cell. The TLC variant of the earlier 128-layer generation was christened X2-9060, while the QLC version is X2-6070.
As with the previous generations of YMTC, the so-called xtacking technology is used: The chip logic (I/O) and memory area are first manufactured separately on separate wafers and only later combined to form a memory chip; YMTC speaks of “hybrid bonding”. Although two wafers are therefore required, the overall costs should not increase, since in this way the storage density can be optimized to such an extent that the additional wafer is worthwhile.
YMTC does not put layer in mouth
What is now changing in detail with the third version called Xtacking 3.0 remains hidden for the time being. To the surprise of many, this also applies to the specification of the number of superimposed levels (layers) with memory cells, which is particularly important in marketing. It is unclear why YMTC is hiding this for the time being. It is possible that this is significantly lower than the competitors Micron with 232 layers and SK Hynix with 238 layers, and this fact should not be put too much in the limelight.
Ultimately, YMTC could have 192 layers, because DigiTimes reported in May that corresponding samples were being delivered. A month later, however, came the report that YMTC would skip the 192-layer generation in favor of the 232-layer generation. So far, however, there has been no official confirmation of this.
ONFI 5.0 with 2,400 MT/s and 6-plane design
However, YMTC gives other details about the new TLC-3D-NAND alias X3-9070. As with the innovations from Micron and SK Hynix, the NAND interface should be accelerated to 2,400 MT/s (ONFI 5.0) and thus increase by 50 percent compared to the predecessor. As with Micron, the TLC NAND is said to store 1 terabit, whereas previously 512 Gbit was common and 1 Tbit chips were only found on QLC NAND with 4 bits per cell. YMTC speaks of the highest bit density in the company's recent history. Without specifying the chip size, however, this cannot be calculated.
In addition to the faster interface, the change to a 6-plane design should ensure more performance. Compared to the 4-plane design, the performance should increase by up to 50 percent, while the power consumption can be reduced by 25 percent at the same time. With its 232-layer NAND, Micron presented a 6-plane design for TLC-NAND for the first time.
Development status unknown
The company's press release does not reveal how far the new 3D NAND generation from YMTC has progressed in terms of market maturity. So it remains to be seen when series production will begin.
Reports about “interference fire” from the USA
Even before the announcement of YMTC had reported to Reuters that the US government is considering restricting shipments of equipment that manufactures memory chips with more than 128 layers in China. This is intended to slow down Chinese advances in the semiconductor sector in order to protect US companies such as Micron and Western Digital, it said. YMTC would be particularly affected by such a measure, but Samsung and SK Hynix also have NAND flash factories in China.