The two Chinese manufacturers DeepComputing and Xcalibyte, led by RISC-V International, have announced the first notebook primarily aimed at developers with the open instruction set architecture RISC-V. The working device christened Roma also relies on up to 16 GB LPDDR4X as well as a GPU and NPU.
The first of its kind especially for developers
The Roma is said to be the first notebook of its kind and, in addition to a previously unreleased quad-core RISC-V CPU with its own security enclave, a security subsystem based on the ARM SecurCore SC300, on up to 16 GB of RAM Put type LPDDR4X and 256 GB flash memory. RISC-V-capable Linux distributions are used as the operating system.
- RISC-V CPU < ul class="text-ul text-width">
- Quad-Core Processor
- ARM SecurCore SC300 (“Security Enclave”)
For more information, see the RISC-V International official blog.
Limited tool with own NFT
The first edition of the RISC-V notebook can be pre-ordered soon and is limited to 100 copies, each of which is also marked with an individual Non-Fungible Token (NFT).
A Web3-friendly platform with NFT creation and publication plus integrated MetaMask-style wallet, ROMA will create an even more integrated experience with future AR glasses and AI speakers operating entirely on RISC-V software and powered by RISC-V hardware.
Xcalibyte
Registration for the pre-sale is possible via the Xcalibyte website. However, Xcalibyte and DeepComputing have not yet provided any information on the expected sales price and the availability of the developer's notebook.
The Roma with RISC-V CPU will start pre-order soon (Image: Xcalibyte /DeepComputing)
The developer tool is initially only intended for the Chinese market and, if it is successful, it will be released in larger quantities and for other regions.
Profound knowledge on RISC-V and ISA
The community from the ComputerBase forum also provides background knowledge on the open source architecture RISC-V and the free Instruction Set Architecture (ISA). .
In the reader's article “Why the world needs a free Instruction Set Architecture!”, community member “TomH22” goes into the background of the RISC-V architecture, whose declared goal is to establish an open standard.
The aim here is to dispense with a complex instruction set that is convenient for assembler programming and instead to work with instructions that are easy to decode and can be executed particularly quickly, as well as a high clock rate.
< ul class="text-ul text-width">
The lively participation of ComputerBase readers in the associated survey in which more than 3,000 votes were cast underlines the great interest in this topic within the community.
- The x86 architecture will prevail for a very long time 19.7%
- Both Architectures will coexist for a long time to come 40.4%
- The ARM architecture will sooner or later replace the x86 architecture 26.3%
- RISC-V could also have a say in the future 13.6 %
3,303 participants + 429 abstentions • Final result