In the released Developer Guide, Intel has given further technical details on the new Alder Lake CPU and special configurations. In addition to the variants already mentioned in the rumors for the desktop without “atomic cores”, the notebook lineup is also confirmed. There are also other small details.
The Developer Guide was made available by Intel on the website and is therefore available to everyone. It is intended to anticipate the upcoming launch, which will take place on October 27th, and thus bring out a little more depth of detail in some points.
Among other things, Intel had really planned that the performance cores (P-Cores) could offer AVX-512 when the efficiency cores (E-Cores) are deactivated – that's what the guide still calls it today. Because the P-Cores aka Golden Cove master this function because they are also used in the server environment.
But since the supported features are based on the lowest common denominator, as with the predecessor Lakefield, in this case the e-cores, the feature will be deactivated in the desktop and notebook. Ultimately, Intel decided that this function does not even exist in the desktop, even if the e-cores are deactivated, as the manufacturer announced at Alder Lake's Architecture Day.
The big topic is the hardware scheduler
A large part of the guide is of course dedicated to the new Intel Thread Director (ITD) as a hardware scheduler, which will take on the task of giving the operating system sensible specifications as to which process should run best on which core or thread. Many parameters are taken into account.
Per Class ID and Perf Capabilities provide relative performance levels of LP Performance vs. Efficient cores. Higher values here indicate higher performance. Per Class ID, EE Capability provides the relative energy efficiency level of an LP. Higher values here indicate higher EE to be used for threads with energy efficiency needs. The OS can choose between EE and performance, depending on parameters such as power policy, battery slider, etc.
Various classes here indicate performance differences between the cores. For example, Class 1 indicates ISA such as AVX2-FP32 where P-cores offer higher performance than E-cores, while Class 2 indicates higher VNNI performance difference. Intel also introduced a class to track waits, such as UMWAIT/TPAUSE, etc., so Performance cores don't sit idle while real work goes to Efficient cores.
The guide also gives instructions on how to implement good and optimal specifications. The developer can determine which applications should run on the e-cores with priority. If this is only implemented in a rudimentary way, Alder Lake behaves like a normal processor with many threads, which, guided by the operating system, gives incorrect assignments here and there and cores are not optimally utilized or overhead forms, which in the end does not represent the optimal performance.
On the desktop even without an Atom
Intel had already officially named three different CPU dies, now The desktop version Alder Lake-S is also clear, which does not use e-cores. This is likely to be used in a Core i5-12400F, among other things, the fourth processor of the Core models, which are always extremely well positioned in their segment and which have hardly had any competition since the Core i5-9400F.
The Core i5 in this class can then access the entire L3 cache and does not have to share it with the e-cores – which are still actually called Atom (A) at Intel. Because as the diagram and the guide make clear once again, only the L3 cache is shared, all other resources are independently available to the cores or the core cluster at Gracemont.
What Alder Lake-S in the end really can, tests will show. Intel itself has set the bar high with performance forecasts of up to 19 percent more performance than Rocket Lake, so expectations are now falling accordingly. This will be finally clarified at the beginning of November.