Toshiba has announced the development of a soc with 64 cores for embedded applications. The (40 nm) chip is composed of two clusters of 32 cores, and has dedicated hardware for image processing on board.
The new Toshiba-soc is produced on a (40 nm)-lp-process with eight copper layers for interconnect. The chip has a total area of 210mm2, while the two 32core-clusters each 42mm2 them to take. The clock speed of the clusters is set at 333MHz, which in total is 1.5 Tops can be calculated. This is fourteen times as much as the octocore-soc that Toshiba for the first time at the ISSCC 2008-trade fair announced. The chip was made using a 65nm process.
Except by use of a smaller process, Toshiba has the energy consumption of the 64core-soc in other ways kept low. This allows unused parts of the chip be disabled, and allows Toshiba to use its own, low-power data-mapping flip-flop circuit. Also, the chip includes hardware to enable the playback of video content to accelerate. The decoding of a h264-1080/30p movie would, therefore, only a capacity of 500mW opslurpen. For the communication between the cores is use of network on a chip technology.
Toshiba wants to be the new ‘many-core soc bets for the automotive industry, but also for consumer products. For this purpose, Toshiba has special hardware for image recognition integrated on the chip. Also, the chip 4k2k video content with a frame rate of 15fps with a consumption of less than 800mW. Toshiba gives more details about the chip at the 2012 IEEE Symposia on VLSI Technology and Circuits, from 12 to 14 June took place in Honolulu.
