During a meeting in Japan, TSMC roadmap for chipproductie shown. The Taiwanese manufacturer will begin next year with the testproductie of chips on 20nm. Two years later, a 14nm-proced lwa to follow.
In the past quarter, the Taiwan Semiconductor Manufacturing Company, better known as TSMC, the development of its 28nm process for mobile chips and it started with the testproductie of these processors according to his CLN28HPM process. Next year, in the third quarter of 2012, the company expects to commence with his high performance process for 20nm chips, either the CLN20G process. The company will start with testproductie, before the process for mass production.
The low-powervariant of the 20nm process should be in January 2013 to follow. To the 20nm process, where the gate density twice as high as in the 28nm process, TSMC use of a number of innovative techniques. For lithography the company deploys a combination of ArF-immersielithografie and double patterning. The electron mobility in the transistors with strained silicon increases and a second generation hkmg replaces the gate-diëlektrum and the gates. In 2014 or early 2015 then the first 14nm processes to be tested. It would finfets, or transistors with different gates, to be introduced and would TSMC may be ArF-immersielithografie continue to use it. The alternative patterningmethodes with euv, and electron beams would yet too little wafers per hours.
For the episode of chips, or the ‘packaging’, focuses TSMC for 2012 on the combining of identical chips on a substrate. That is a technique that is as homogeneous 2D-packing’ is known. By 2013 or 2014 must have different chips with each other in a 2d structure, or heterogeneous 2D-technique, are combined. TSMC would then, for example, complete soc’s can provide. Not earlier than in 2014 would TSMC three-dimensional chipverpakkingen supply, with several chips stacked together.
